Date added: June 26, 2018
Affected Products: TAM-3517 , THB-3517
Changing memory timings
The TI OMAP3 based product lines (includes Sitara and DaVinci processors) have their memory parameters controlled by X-loader.
X-loader is a small stripped down u-boot (similar to the later SPL) that can fit in on chip RAM and initialize memory and load u-boot. In TechNexion source code (X-loader 1.51), the memory timings are initialized in board/tam3517/tam3517.c
The most important register is EMIF4_CFG, and the most important parameter (as of 2018) is the memory driving strength, defined by the constant EMIF4_CFG_SDR_DRV. The default value is 0x0 for normal drive strength, but a reduced setting can be achieved by setting the drive strength to 0x1. Note that the values 0x2 and 0x3 are not applicable on the TAM-3517.
The default setting is high drive strength for commercial memory (pre 2018).
In general one should use a lower drive strength (SDR_DRV == 0x1) in low temperature operations.
Applying updated memory timings
To apply the changes, re-compile X-loader.
Since ARM toolchains are notorios for not producing correct code (actually this is more due to u-boot and the like having dependences on undefined behaviour), it is important to use a toolchain that is know good.
The gold standard toolchain for the OMAP3 line is gcc-4.5.1, codesourcery 2010 edition, downloadable from ftp://ftp.technexion.net/development_resources/development_tools/gcc/gcc-4.5.1-arm-codesourcery-2010.09-50.tar.xz
The X-loader is compiled by:
Configuration: % make tam3517_config
Build: % make -j4
Install by copying the X-loader binary (named “MLO”) to an SD card. Note: the file should be the first file in the first, FAT formatted partition. It usually suffices to replace an existing MLO. Check the boot message that the compile date matches what is expected!
Validating memory timings
There are a few tests to for validating the memory settings on TAM-3517.